Automating Relatively Complete Verification of Higher-Order Functional Programs Hiroshi Unno Tachio Terauchi

Source URL: www.cs.tsukuba.ac.jp

Automating Relatively Complete Verification of Higher-Order Functional Programs Hiroshi Unno Tachio Terauchi

Source URL: www.cs.tsukuba.ac.jp

A Logic Programming Approach to the Verification ∗ of Functional-Logic Programs Jose´ Miguel Cleva

Source URL: gpd.sip.ucm.es

Functional Genomics Research Stream Research Meetings: September 7 & 8, 2009 TAP Strains, ChIP Process & Verification Topics

Source URL: fg.cns.utexas.edu

Formal verification of a realistic compiler Xavier Leroy INRIA Paris-Rocquencourt Domaine de Voluceau, B.P. 105, 78153 Le Chesnay, France

Source URL: cristal.inria.fr

• Compilers
• Programming language implementation
• Functional languages
• Formal methods
• Compiler correctness
• Compiler
• Compcert
• Xavier Leroy
• Code generation
• Software
• Computing
• Compiler construction

Corporate and Product Overview Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing ve

Source URL: realintent.com

• Electronic design
• Hardware verification languages
• Logic design
• Logic simulation
• Functional verification
• Design closure
• E
• Formal verification
• Application-specific integrated circuit
• Electronic engineering
• Digital electronics
• Electronic design automation

1/ Toccata Toccata Deductive Verification, Certified Tools and Numerical Computations

Source URL: vals.lri.fr

• Formal methods
• Functional languages
• Logic in computer science
• Theoretical computer science
• Automated theorem proving
• Formal verification
• SIGNAL
• Coq
• National Institute for Research in Computer Science and Control
• Computing
• Software engineering
• Software

ALINT-PRO-CDC™ CDC Verification Static Structural Verification Clock Domain Crossing Verification ALINT-PRO-CDC™ is a design verification solution from Aldec which enables verification of clock domain crossings and

Source URL: www.aldec.com

• Hardware verification languages
• Aldec
• Electronic design
• SystemVerilog
• E
• Clock domain crossing
• Verilog
• VHDL
• Functional verification
• Electronic engineering
• Electronic design automation
• Hardware description languages

Manuel Hermenegildo Areas of Interest Energy-Aware Computing, Resource / non-functional property analysis, verification, and control; Global Program Analysis, Optimization, Verification, Debugging; Abstract Interpretatio

Source URL: www.clip.dia.fi.upm.es

• Programming paradigms
• Formal sciences
• Association for Computing Machinery
• Principles of Programming Languages
• Formal methods
• International Conference on Logic Programming
• Logic programming
• International Symposium on Logic-based Program Synthesis and Transformation
• Lecture Notes in Computer Science
• Computer science
• Computing
• Software engineering

Full Functional Verification of Linked Data Structures Karen Zee Viktor Kuncak Martin C. Rinard

Source URL: lara.epfl.ch

• Automated theorem proving
• Formal methods
• Logic in computer science
• Model theory
• KeY
• First-order logic
• Isabelle
• Formal verification
• Predicate transformer semantics
• Mathematics
• Theoretical computer science
• Mathematical logic